--
-- VHDL Architecture Fietscomputer_lib.bin2zeven_segment.v
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp7985)
--          at - 13:57:48 23-09-2009
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY s_bin2zeven_segment IS
   PORT (
      bin           : IN     STD_LOGIC_VECTOR(3 DOWNTO 0);
      zeven_segment : OUT    STD_LOGIC_VECTOR(7 DOWNTO 0)
   );
END s_bin2zeven_segment;

--
ARCHITECTURE v OF s_bin2zeven_segment IS
BEGIN
  
    PROCESS(bin)
      BEGIN
      CASE bin IS
             WHEN "0000" => zeven_segment <= NOT ('0' & b"111_1110");
             WHEN "0001" => zeven_segment <= NOT ('0' & b"011_0000");
             WHEN "0010" => zeven_segment <= NOT ('0' & b"110_1101");
             WHEN "0011" => zeven_segment <= NOT ('0' & b"111_1001");
             WHEN "0100" => zeven_segment <= NOT ('0' & b"011_0011");
             WHEN "0101" => zeven_segment <= NOT ('0' & b"101_1011");
             WHEN "0110" => zeven_segment <= NOT ('0' & b"101_1111");
             WHEN "0111" => zeven_segment <= NOT ('0' & b"111_0000");
             WHEN "1000" => zeven_segment <= NOT ('0' & b"111_1111");
             WHEN "1001" => zeven_segment <= NOT ('0' & b"111_1011");
             WHEN "1010" => zeven_segment <= NOT ('0' & b"111_0111");
             WHEN "1011" => zeven_segment <= NOT ('0' & b"001_1111");
             WHEN "1100" => zeven_segment <= NOT ('0' & b"000_1101");
             WHEN "1101" => zeven_segment <= NOT ('0' & b"011_1101");
             WHEN "1110" => zeven_segment <= NOT ('0' & b"100_1111");
             WHEN OTHERS => zeven_segment <= NOT ('0' & b"100_0111");   
         END CASE;  
       END PROCESS;
    
    

  
  
END ARCHITECTURE v;

